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EM250
further reception is dropped and the register bit SC_SPIRXOVF in the SC1_SPISTAT register is set. The RX
FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear
the error indication: setting the appropriate SC_TX/RXDMARST bit in the SC1_DMACTRL register, or loading the
appropriate DMA buffer after it has unloaded.
Receiving a character always requires transmitting a character. In a case when a long stream of receive
characters is expected, a long sequence of (dummy) transmit characters must be generated. To avoid
software or transmit DMA initiating these transfers (and consuming unnecessary bandwidth), the SPI serializer
can be instructed to retransmit the last transmitted character, or to transmit a busy token ( 0xFF ), which is
determined by the register bit SC_SPIRPT in the SC1_SPICFG register. This functionality can only be enabled
(or disabled) when the transmit FIFO is empty and the transmit serializer is idle, as indicated by a cleared
SC_SPITXIDLE register bit in the SC1_SPISTAT register.
Every time an automatic character transmission is started, a transmit underrun is detected (as there is no data
in transmit FIFO), and the register bit INT_SCTXUND in the INT_SC1FLAG register is set. Note that after
disabling the automatic character transmission, the reception of new characters stops and the receive FIFO
holds characters just received.
Note:
The event Receive DMA complete does not automatically mean receive FIFO empty.
Interrupts are generated on the following events:
?
?
?
?
?
?
?
Transmit FIFO empty and last character shifted out (0 to 1 transition of SC_SPITXIDLE )
Transmit FIFO changed from full to not full (0 to 1 transition of SC_SPITXFREE )
Receive FIFO changed from empty to not empty (0 to 1 transition of SC_SPIRXVAL )
Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B )
Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B )
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
To generate interrupts to the CPU, the interrupt masks in the INT_SC1CFG and INT_CFG registers must be
enabled.
5.2.3
I 2 C Master Mode
The SC1 I 2 C controller is only available in master mode. The SC1 I 2 C controller is enabled with SC1_MODE set to
3. The I 2 C Master controller supports Standard (100kbps) and Fast (400kbps) I 2 C modes. Address arbitration is
not implemented, so multiple master applications are not supported. The I 2 C signals are pure open-collector
signals, and external pull-up resistors are required.
The SC1 I 2 C mode has the following features:
?
?
Programmable clock frequency (400kHz max.)
Supports both 7-bit and 10-bit addressing
The following signals can be made available on the GPIO pins:
?
?
MSDA (serial data)
MSCL (serial clock)
The I 2 C Master controller obtains its reference clock from a programmable clock generator. Clock rates are set
by a clock division ratio from the 24MHz clock:
Nominal Rate = 24MHz / ( 2 * (LIN + 1) * 2 EXP )
120-0082-000V Rev 1.1
Page 44
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